The inventive concepts described herein are generally related to a semiconductor memory device, and more particularly to a semiconductor memory device that provides effective testing of the memory, and a system including the semiconductor memory device.
As semiconductor memory devices become more highly integrated, the memory capacity of semiconductor memory devices has rapidly increased. The increased memory capacity is in part due to the development of semiconductor manufacturing techniques, which enables an increase of the number of memory cells included in one chip. However, as the number of total memory cells increases, the number of failed memory cells may increase also. Even a single failed memory cell may result in a critical defect in a semiconductor memory device. Failed memory cells should thus be replaced with the normal memory cells. Semiconductor memory devices typically include redundant memory cells to be substituted for failed memory cells based on fail information.
In general, the type of testing techniques needed to test a semiconductor device is a design/production concern that may be as considerable as improving density and complexity of the semiconductor device itself. Reduction of time and cost as well as improvement of testability may be required for mass production of a semiconductor memory device. Thus, there is a need for a design-for-test (DFT) scheme for improving efficiency of testing during a design phase of the semiconductor memory device.